
create_clock -period 40.000 -name clk_out25_clk_wiz_regmap0 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[0].pcie0/clk0/clk0/inst/clock_primitive_inst/*/CLKOUT0"}]
#create_generated_clock -name clk_out25_clk_wiz_regmap0 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[0].pcie0/clk0/clk0/inst/clock_primitive_inst/*/CLKOUT0"}]
#create_generated_clock -name pcie_userclk0 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[0].pcie0/ep0/g_NoSim.g_versal.pcie_ep_versal0/versal_cips_block_i/versal_cips_0/U0/DPLL_PCIE0_inst/CLKOUT0"}]
create_clock -period 40.000 -name clk_out25_clk_wiz_regmap1 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[1].pcie0/clk0/clk0/inst/clock_primitive_inst/*/CLKOUT0"}]
#create_generated_clock -name clk_out25_clk_wiz_regmap1 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[1].pcie0/clk0/clk0/inst/clock_primitive_inst/*/CLKOUT0"}]
#create_generated_clock -name pcie_userclk1 [get_pins -hierarchical -filter {NAME =~ "g_endpoints[1].pcie0/ep0/g_NoSim.g_versal.pcie_ep_versal0/versal_cips_block_i/versal_cips_0/U0/DPLL_PCIE0_inst/CLKOUT0"}]

set_property PACKAGE_PIN BN27 [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property PACKAGE_PIN BM27 [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property PACKAGE_PIN BK27 [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property PACKAGE_PIN BL26 [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property PACKAGE_PIN BM26 [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property PACKAGE_PIN BJ25 [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property PACKAGE_PIN BN26 [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property PACKAGE_PIN BH25 [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property PACKAGE_PIN BB28 [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property PACKAGE_PIN BC29 [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property PACKAGE_PIN BB30 [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property PACKAGE_PIN BC30 [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property PACKAGE_PIN AY29 [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property PACKAGE_PIN BD28 [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property PACKAGE_PIN BA28 [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property PACKAGE_PIN BE28 [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property PACKAGE_PIN BK26 [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property PACKAGE_PIN BL25 [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property PACKAGE_PIN BB27 [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property PACKAGE_PIN BC28 [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property PACKAGE_PIN BM28 [get_ports {LPDDR_out[1]ca_a[0]}]
set_property PACKAGE_PIN BL28 [get_ports {LPDDR_out[1]ca_a[1]}]
set_property PACKAGE_PIN BK31 [get_ports {LPDDR_out[1]ca_a[2]}]
set_property PACKAGE_PIN BL29 [get_ports {LPDDR_out[1]ca_a[3]}]
set_property PACKAGE_PIN BM31 [get_ports {LPDDR_out[1]ca_a[4]}]
set_property PACKAGE_PIN BN31 [get_ports {LPDDR_out[1]ca_a[5]}]
set_property PACKAGE_PIN BK30 [get_ports LPDDR_out[1]cs_a]
set_property PACKAGE_PIN BL30 [get_ports LPDDR_inout[1]ck_t_a]
set_property PACKAGE_PIN BM29 [get_ports LPDDR_inout[1]ck_c_a]
set_property PACKAGE_PIN BN29 [get_ports LPDDR_out[1]cke_a]
set_property PACKAGE_PIN BG26 [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property PACKAGE_PIN AY30 [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property PACKAGE_PIN BB26 [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property PACKAGE_PIN BA25 [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property PACKAGE_PIN BC25 [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property PACKAGE_PIN AY26 [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property PACKAGE_PIN BD24 [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property PACKAGE_PIN BE25 [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property PACKAGE_PIN AV25 [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property PACKAGE_PIN AW26 [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property PACKAGE_PIN AW29 [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property PACKAGE_PIN AV30 [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property PACKAGE_PIN AY27 [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property PACKAGE_PIN AU29 [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property PACKAGE_PIN AU27 [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property PACKAGE_PIN AT28 [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property PACKAGE_PIN AV28 [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property PACKAGE_PIN BA27 [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property PACKAGE_PIN AY24 [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property PACKAGE_PIN AW25 [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property PACKAGE_PIN AT29 [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property PACKAGE_PIN AU30 [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property PACKAGE_PIN BF27 [get_ports {LPDDR_out[1]ca_b[0]}]
set_property PACKAGE_PIN BK28 [get_ports {LPDDR_out[1]ca_b[1]}]
set_property PACKAGE_PIN BJ30 [get_ports {LPDDR_out[1]ca_b[2]}]
set_property PACKAGE_PIN BH30 [get_ports {LPDDR_out[1]ca_b[3]}]
set_property PACKAGE_PIN BJ29 [get_ports {LPDDR_out[1]ca_b[4]}]
set_property PACKAGE_PIN BH29 [get_ports {LPDDR_out[1]ca_b[5]}]
set_property PACKAGE_PIN AW28 [get_ports LPDDR_out[1]cs_b]
set_property PACKAGE_PIN BH27 [get_ports LPDDR_out[1]ck_t_b]
set_property PACKAGE_PIN BJ27 [get_ports LPDDR_inout[1]ck_c_b]
set_property PACKAGE_PIN BJ28 [get_ports LPDDR_out[1]cke_b]
set_property PACKAGE_PIN AT26 [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property PACKAGE_PIN AV27 [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property PACKAGE_PIN BE29 [get_ports LPDDR_out[1]reset_n]
set_property PACKAGE_PIN AY18 [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property PACKAGE_PIN BA18 [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property PACKAGE_PIN BB19 [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property PACKAGE_PIN BB20 [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property PACKAGE_PIN BB22 [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property PACKAGE_PIN BC21 [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property PACKAGE_PIN AY20 [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property PACKAGE_PIN BA21 [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property PACKAGE_PIN BN24 [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property PACKAGE_PIN BJ23 [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property PACKAGE_PIN BK23 [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property PACKAGE_PIN BN25 [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property PACKAGE_PIN BL24 [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property PACKAGE_PIN BM24 [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property PACKAGE_PIN BK25 [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property PACKAGE_PIN BJ24 [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property PACKAGE_PIN AY21 [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property PACKAGE_PIN BA22 [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property PACKAGE_PIN BG24 [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property PACKAGE_PIN BH24 [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property PACKAGE_PIN AU18 [get_ports {LPDDR_out[3]ca_a[0]}]
set_property PACKAGE_PIN AT19 [get_ports {LPDDR_out[3]ca_a[1]}]
set_property PACKAGE_PIN AV21 [get_ports {LPDDR_out[3]ca_a[2]}]
set_property PACKAGE_PIN AU20 [get_ports {LPDDR_out[3]ca_a[3]}]
set_property PACKAGE_PIN AV22 [get_ports {LPDDR_out[3]ca_a[4]}]
set_property PACKAGE_PIN AW22 [get_ports {LPDDR_out[3]ca_a[5]}]
set_property PACKAGE_PIN AT20 [get_ports LPDDR_out[3]cs_a]
set_property PACKAGE_PIN AV18 [get_ports LPDDR_out[3]ck_t_a]
set_property PACKAGE_PIN AW19 [get_ports LPDDR_inout[3]ck_c_a]
set_property PACKAGE_PIN AV19 [get_ports LPDDR_out[3]cke_a]
set_property PACKAGE_PIN BA19 [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property PACKAGE_PIN BL23 [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property PACKAGE_PIN BM21 [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property PACKAGE_PIN BK21 [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property PACKAGE_PIN BL19 [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property PACKAGE_PIN BN22 [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property PACKAGE_PIN BM22 [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property PACKAGE_PIN BM19 [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property PACKAGE_PIN BL20 [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property PACKAGE_PIN BN21 [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property PACKAGE_PIN BB23 [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property PACKAGE_PIN BA24 [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property PACKAGE_PIN BB24 [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property PACKAGE_PIN AU23 [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property PACKAGE_PIN AV24 [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property PACKAGE_PIN BC24 [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property PACKAGE_PIN AT25 [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property PACKAGE_PIN AU24 [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property PACKAGE_PIN BN19 [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property PACKAGE_PIN BN20 [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property PACKAGE_PIN AW23 [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property PACKAGE_PIN AY23 [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property PACKAGE_PIN BJ20 [get_ports {LPDDR_out[3]ca_b[0]}]
set_property PACKAGE_PIN BK20 [get_ports {LPDDR_out[3]ca_b[1]}]
set_property PACKAGE_PIN BH22 [get_ports {LPDDR_out[3]ca_b[2]}]
set_property PACKAGE_PIN BJ22 [get_ports {LPDDR_out[3]ca_b[3]}]
set_property PACKAGE_PIN BH21 [get_ports {LPDDR_out[3]ca_b[4]}]
set_property PACKAGE_PIN BG21 [get_ports {LPDDR_out[3]ca_b[5]}]
set_property PACKAGE_PIN BB18 [get_ports LPDDR_out[3]cs_b]
set_property PACKAGE_PIN BH20 [get_ports LPDDR_out[3]ck_t_b]
set_property PACKAGE_PIN BJ19 [get_ports LPDDR_inout[3]ck_c_b]
set_property PACKAGE_PIN BG22 [get_ports LPDDR_out[3]cke_b]
set_property PACKAGE_PIN BK22 [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property PACKAGE_PIN AT22 [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property PACKAGE_PIN BF28 [get_ports LPDDR_out[3]reset_n]
set_property PACKAGE_PIN BD30 [get_ports lpddr4_clk2_clk_p]
set_property PACKAGE_PIN BE30 [get_ports lpddr4_clk2_clk_n]
set_property PACKAGE_PIN BM4 [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property PACKAGE_PIN BN5 [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property PACKAGE_PIN BM7 [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property PACKAGE_PIN BN7 [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property PACKAGE_PIN BL6 [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property PACKAGE_PIN BK7 [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property PACKAGE_PIN BL5 [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property PACKAGE_PIN BL8 [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property PACKAGE_PIN BE18 [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property PACKAGE_PIN BF18 [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property PACKAGE_PIN BC16 [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property PACKAGE_PIN BD16 [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property PACKAGE_PIN BB14 [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property PACKAGE_PIN BE17 [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property PACKAGE_PIN BB15 [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property PACKAGE_PIN BF16 [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property PACKAGE_PIN BM6 [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property PACKAGE_PIN BN6 [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property PACKAGE_PIN BD15 [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property PACKAGE_PIN BE16 [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property PACKAGE_PIN BL15 [get_ports {LPDDR_out[0]ca_a[0]}]
set_property PACKAGE_PIN BK16 [get_ports {LPDDR_out[0]ca_a[1]}]
set_property PACKAGE_PIN BK17 [get_ports {LPDDR_out[0]ca_a[2]}]
set_property PACKAGE_PIN BN17 [get_ports {LPDDR_out[0]ca_a[3]}]
set_property PACKAGE_PIN BM17 [get_ports {LPDDR_out[0]ca_a[4]}]
set_property PACKAGE_PIN BN16 [get_ports {LPDDR_out[0]ca_a[5]}]
set_property PACKAGE_PIN BM18 [get_ports LPDDR_out[0]cs_a]
set_property PACKAGE_PIN BM14 [get_ports LPDDR_out[0]ck_t_a]
set_property PACKAGE_PIN BN14 [get_ports LPDDR_inout[0]ck_c_a]
set_property PACKAGE_PIN BM16 [get_ports LPDDR_out[0]cke_a]
set_property PACKAGE_PIN BN9 [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property PACKAGE_PIN BB16 [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property PACKAGE_PIN BL11 [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property PACKAGE_PIN BN12 [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property PACKAGE_PIN BL10 [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property PACKAGE_PIN BM12 [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property PACKAGE_PIN BJ10 [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property PACKAGE_PIN BK10 [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property PACKAGE_PIN BJ12 [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property PACKAGE_PIN BK11 [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property PACKAGE_PIN BA16 [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property PACKAGE_PIN AY17 [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property PACKAGE_PIN AY15 [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property PACKAGE_PIN AV16 [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property PACKAGE_PIN AU15 [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property PACKAGE_PIN AT16 [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property PACKAGE_PIN AW17 [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property PACKAGE_PIN BA15 [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property PACKAGE_PIN BM11 [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property PACKAGE_PIN BN11 [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property PACKAGE_PIN AT17 [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property PACKAGE_PIN AU17 [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property PACKAGE_PIN BH14 [get_ports {LPDDR_out[0]ca_b[0]}]
set_property PACKAGE_PIN BL14 [get_ports {LPDDR_out[0]ca_b[1]}]
set_property PACKAGE_PIN BJ17 [get_ports {LPDDR_out[0]ca_b[2]}]
set_property PACKAGE_PIN BH16 [get_ports {LPDDR_out[0]ca_b[3]}]
set_property PACKAGE_PIN BL18 [get_ports {LPDDR_out[0]ca_b[4]}]
set_property PACKAGE_PIN BK18 [get_ports {LPDDR_out[0]ca_b[5]}]
set_property PACKAGE_PIN AW16 [get_ports LPDDR_out[0]cs_b]
set_property PACKAGE_PIN BH15 [get_ports LPDDR_out[0]ck_t_b]
set_property PACKAGE_PIN BJ15 [get_ports LPDDR_inout[0]ck_c_b]
set_property PACKAGE_PIN BK15 [get_ports LPDDR_out[0]cke_b]
set_property PACKAGE_PIN BL13 [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property PACKAGE_PIN AV15 [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property PACKAGE_PIN BF14 [get_ports LPDDR_out[0]reset_n]
set_property PACKAGE_PIN AP11 [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property PACKAGE_PIN AR12 [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property PACKAGE_PIN AU14 [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property PACKAGE_PIN AV13 [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property PACKAGE_PIN AT13 [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property PACKAGE_PIN AT14 [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property PACKAGE_PIN AP12 [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property PACKAGE_PIN AR13 [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property PACKAGE_PIN BJ2 [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property PACKAGE_PIN BJ5 [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property PACKAGE_PIN BK5 [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property PACKAGE_PIN BK2 [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property PACKAGE_PIN BJ3 [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property PACKAGE_PIN BK3 [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property PACKAGE_PIN BL3 [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property PACKAGE_PIN BL4 [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property PACKAGE_PIN AN14 [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property PACKAGE_PIN AP15 [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property PACKAGE_PIN BJ7 [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property PACKAGE_PIN BK6 [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property PACKAGE_PIN AJ13 [get_ports {LPDDR_out[2]ca_a[0]}]
set_property PACKAGE_PIN AJ12 [get_ports {LPDDR_out[2]ca_a[1]}]
set_property PACKAGE_PIN AM15 [get_ports {LPDDR_out[2]ca_a[2]}]
set_property PACKAGE_PIN AL15 [get_ports {LPDDR_out[2]ca_a[3]}]
set_property PACKAGE_PIN AL14 [get_ports {LPDDR_out[2]ca_a[4]}]
set_property PACKAGE_PIN AM13 [get_ports {LPDDR_out[2]ca_a[5]}]
set_property PACKAGE_PIN AJ15 [get_ports LPDDR_out[2]cs_a]
set_property PACKAGE_PIN AK13 [get_ports LPDDR_out[2]ck_t_a]
set_property PACKAGE_PIN AL12 [get_ports LPDDR_inout[2]ck_c_a]
set_property PACKAGE_PIN AM12 [get_ports LPDDR_out[2]cke_a]
set_property PACKAGE_PIN AP14 [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property PACKAGE_PIN BH4 [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property PACKAGE_PIN BE9 [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property PACKAGE_PIN BA10 [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property PACKAGE_PIN BC12 [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property PACKAGE_PIN BE10 [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property PACKAGE_PIN BD10 [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property PACKAGE_PIN BD11 [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property PACKAGE_PIN BB10 [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property PACKAGE_PIN BF10 [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property PACKAGE_PIN BH11 [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property PACKAGE_PIN BG12 [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property PACKAGE_PIN BG10 [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property PACKAGE_PIN BE12 [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property PACKAGE_PIN BF11 [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property PACKAGE_PIN BH10 [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property PACKAGE_PIN BG13 [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property PACKAGE_PIN BH12 [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property PACKAGE_PIN BC9 [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property PACKAGE_PIN BC10 [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property PACKAGE_PIN BG9 [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property PACKAGE_PIN BH9 [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property PACKAGE_PIN BA12 [get_ports {LPDDR_out[2]ca_b[0]}]
set_property PACKAGE_PIN BB11 [get_ports {LPDDR_out[2]ca_b[1]}]
set_property PACKAGE_PIN AY12 [get_ports {LPDDR_out[2]ca_b[2]}]
set_property PACKAGE_PIN BB12 [get_ports {LPDDR_out[2]ca_b[3]}]
set_property PACKAGE_PIN BA13 [get_ports {LPDDR_out[2]ca_b[4]}]
set_property PACKAGE_PIN AW13 [get_ports {LPDDR_out[2]ca_b[5]}]
set_property PACKAGE_PIN AR15 [get_ports LPDDR_out[2]cs_b]
set_property PACKAGE_PIN AY9 [get_ports LPDDR_out[2]ck_t_b]
set_property PACKAGE_PIN BA9 [get_ports LPDDR_inout[2]ck_c_b]
set_property PACKAGE_PIN AY14 [get_ports LPDDR_out[2]cke_b]
set_property PACKAGE_PIN BC13 [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property PACKAGE_PIN BE13 [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property PACKAGE_PIN BG14 [get_ports LPDDR_out[2]reset_n]
set_property PACKAGE_PIN BG1 [get_ports {PCIE0_GT_0_grx_n[0]}]
set_property PACKAGE_PIN BE1 [get_ports {PCIE0_GT_0_grx_n[1]}]
set_property PACKAGE_PIN BC1 [get_ports {PCIE0_GT_0_grx_n[2]}]
set_property PACKAGE_PIN BB3 [get_ports {PCIE0_GT_0_grx_n[3]}]
set_property PACKAGE_PIN BA1 [get_ports {PCIE0_GT_0_grx_n[4]}]
set_property PACKAGE_PIN AY3 [get_ports {PCIE0_GT_0_grx_n[5]}]
set_property PACKAGE_PIN AW1 [get_ports {PCIE0_GT_0_grx_n[6]}]
set_property PACKAGE_PIN AU1 [get_ports {PCIE0_GT_0_grx_n[7]}]
set_property PACKAGE_PIN BG2 [get_ports {PCIE0_GT_0_grx_p[0]}]
set_property PACKAGE_PIN BE2 [get_ports {PCIE0_GT_0_grx_p[1]}]
set_property PACKAGE_PIN BC2 [get_ports {PCIE0_GT_0_grx_p[2]}]
set_property PACKAGE_PIN BB4 [get_ports {PCIE0_GT_0_grx_p[3]}]
set_property PACKAGE_PIN BA2 [get_ports {PCIE0_GT_0_grx_p[4]}]
set_property PACKAGE_PIN AY4 [get_ports {PCIE0_GT_0_grx_p[5]}]
set_property PACKAGE_PIN AW2 [get_ports {PCIE0_GT_0_grx_p[6]}]
set_property PACKAGE_PIN AU2 [get_ports {PCIE0_GT_0_grx_p[7]}]
set_property PACKAGE_PIN BG6 [get_ports {PCIE0_GT_0_gtx_n[0]}]
set_property PACKAGE_PIN BF4 [get_ports {PCIE0_GT_0_gtx_n[1]}]
set_property PACKAGE_PIN BE6 [get_ports {PCIE0_GT_0_gtx_n[2]}]
set_property PACKAGE_PIN BD4 [get_ports {PCIE0_GT_0_gtx_n[3]}]
set_property PACKAGE_PIN BC6 [get_ports {PCIE0_GT_0_gtx_n[4]}]
set_property PACKAGE_PIN BA6 [get_ports {PCIE0_GT_0_gtx_n[5]}]
set_property PACKAGE_PIN AW6 [get_ports {PCIE0_GT_0_gtx_n[6]}]
set_property PACKAGE_PIN AV4 [get_ports {PCIE0_GT_0_gtx_n[7]}]
set_property PACKAGE_PIN BG7 [get_ports {PCIE0_GT_0_gtx_p[0]}]
set_property PACKAGE_PIN BF5 [get_ports {PCIE0_GT_0_gtx_p[1]}]
set_property PACKAGE_PIN BE7 [get_ports {PCIE0_GT_0_gtx_p[2]}]
set_property PACKAGE_PIN BD5 [get_ports {PCIE0_GT_0_gtx_p[3]}]
set_property PACKAGE_PIN BC7 [get_ports {PCIE0_GT_0_gtx_p[4]}]
set_property PACKAGE_PIN BA7 [get_ports {PCIE0_GT_0_gtx_p[5]}]
set_property PACKAGE_PIN AW7 [get_ports {PCIE0_GT_0_gtx_p[6]}]
set_property PACKAGE_PIN AV5 [get_ports {PCIE0_GT_0_gtx_p[7]}]
set_property PACKAGE_PIN AU6 [get_ports gt_refclk0_0_clk_n]
set_property PACKAGE_PIN AU7 [get_ports gt_refclk0_0_clk_p]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_t_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_t_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_c_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_c_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_c_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_c_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_t_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dqs_t_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dq_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_a[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[2]ca_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[2]ca_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[2]ca_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[2]ca_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[2]ca_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[2]ca_b[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[2]ca_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dmi_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dmi_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dmi_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[2]dmi_b[0]}]
set_property DIRECTION OUT [get_ports LPDDR_inout[2]ck_c_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[2]ck_c_a]
set_property SLEW FAST [get_ports LPDDR_inout[2]ck_c_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[2]ck_c_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[2]ck_c_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[2]ck_c_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[2]ck_c_a]
set_property DIRECTION OUT [get_ports LPDDR_out[2]ck_t_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[2]ck_t_a]
set_property SLEW FAST [get_ports LPDDR_out[2]ck_t_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]ck_t_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]ck_t_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]ck_t_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]ck_t_a]
set_property DIRECTION OUT [get_ports LPDDR_inout[2]ck_c_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[2]ck_c_b]
set_property SLEW FAST [get_ports LPDDR_inout[2]ck_c_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[2]ck_c_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[2]ck_c_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[2]ck_c_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[2]ck_c_b]
set_property DIRECTION OUT [get_ports LPDDR_out[2]ck_t_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[2]ck_t_b]
set_property SLEW FAST [get_ports LPDDR_out[2]ck_t_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]ck_t_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]ck_t_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]ck_t_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]ck_t_b]
set_property DIRECTION OUT [get_ports LPDDR_out[2]cke_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[2]cke_a]
set_property SLEW FAST [get_ports LPDDR_out[2]cke_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]cke_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]cke_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]cke_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]cke_a]
set_property DIRECTION OUT [get_ports LPDDR_out[2]cke_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[2]cke_b]
set_property SLEW FAST [get_ports LPDDR_out[2]cke_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]cke_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]cke_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]cke_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]cke_b]
set_property DIRECTION OUT [get_ports LPDDR_out[2]cs_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[2]cs_a]
set_property SLEW FAST [get_ports LPDDR_out[2]cs_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]cs_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]cs_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]cs_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]cs_a]
set_property DIRECTION OUT [get_ports LPDDR_out[2]cs_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[2]cs_b]
set_property SLEW FAST [get_ports LPDDR_out[2]cs_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]cs_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]cs_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]cs_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]cs_b]
set_property DIRECTION OUT [get_ports LPDDR_out[2]reset_n]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[2]reset_n]
set_property SLEW FAST [get_ports LPDDR_out[2]reset_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[2]reset_n]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[2]reset_n]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[2]reset_n]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[2]reset_n]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_t_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_t_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_c_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_c_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_c_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_c_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_t_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dqs_t_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dq_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_a[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[1]ca_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[1]ca_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[1]ca_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[1]ca_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[1]ca_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[1]ca_b[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[1]ca_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dmi_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dmi_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dmi_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[1]dmi_b[0]}]
set_property DIRECTION OUT [get_ports LPDDR_inout[1]ck_c_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[1]ck_c_a]
set_property SLEW FAST [get_ports LPDDR_inout[1]ck_c_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[1]ck_c_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[1]ck_c_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[1]ck_c_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[1]ck_c_a]
set_property DIRECTION OUT [get_ports LPDDR_out[1]ck_t_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[1]ck_t_a]
set_property SLEW FAST [get_ports LPDDR_out[1]ck_t_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]ck_t_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]ck_t_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]ck_t_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]ck_t_a]
set_property DIRECTION OUT [get_ports LPDDR_inout[1]ck_c_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[1]ck_c_b]
set_property SLEW FAST [get_ports LPDDR_inout[1]ck_c_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[1]ck_c_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[1]ck_c_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[1]ck_c_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[1]ck_c_b]
set_property DIRECTION OUT [get_ports LPDDR_out[1]ck_t_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[1]ck_t_b]
set_property SLEW FAST [get_ports LPDDR_out[1]ck_t_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]ck_t_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]ck_t_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]ck_t_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]ck_t_b]
set_property DIRECTION OUT [get_ports LPDDR_out[1]cke_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[1]cke_a]
set_property SLEW FAST [get_ports LPDDR_out[1]cke_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]cke_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]cke_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]cke_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]cke_a]
set_property DIRECTION OUT [get_ports LPDDR_out[1]cke_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[1]cke_b]
set_property SLEW FAST [get_ports LPDDR_out[1]cke_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]cke_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]cke_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]cke_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]cke_b]
set_property DIRECTION OUT [get_ports LPDDR_out[1]cs_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[1]cs_a]
set_property SLEW FAST [get_ports LPDDR_out[1]cs_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]cs_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]cs_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]cs_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]cs_a]
set_property DIRECTION OUT [get_ports LPDDR_out[1]cs_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[1]cs_b]
set_property SLEW FAST [get_ports LPDDR_out[1]cs_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]cs_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]cs_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]cs_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]cs_b]
set_property DIRECTION OUT [get_ports LPDDR_out[1]reset_n]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[1]reset_n]
set_property SLEW FAST [get_ports LPDDR_out[1]reset_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[1]reset_n]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[1]reset_n]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[1]reset_n]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[1]reset_n]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_t_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_t_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_c_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_c_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_t_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_t_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_c_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dqs_c_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dq_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_a[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[0]ca_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[0]ca_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[0]ca_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[0]ca_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[0]ca_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[0]ca_b[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[0]ca_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dmi_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dmi_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dmi_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[0]dmi_b[0]}]
set_property DIRECTION OUT [get_ports LPDDR_inout[0]ck_c_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[0]ck_c_a]
set_property SLEW FAST [get_ports LPDDR_inout[0]ck_c_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[0]ck_c_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[0]ck_c_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[0]ck_c_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[0]ck_c_a]
set_property DIRECTION OUT [get_ports LPDDR_out[0]ck_t_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[0]ck_t_a]
set_property SLEW FAST [get_ports LPDDR_out[0]ck_t_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]ck_t_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]ck_t_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]ck_t_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]ck_t_a]
set_property DIRECTION OUT [get_ports LPDDR_inout[0]ck_c_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[0]ck_c_b]
set_property SLEW FAST [get_ports LPDDR_inout[0]ck_c_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[0]ck_c_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[0]ck_c_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[0]ck_c_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[0]ck_c_b]
set_property DIRECTION OUT [get_ports LPDDR_out[0]ck_t_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[0]ck_t_b]
set_property SLEW FAST [get_ports LPDDR_out[0]ck_t_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]ck_t_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]ck_t_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]ck_t_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]ck_t_b]
set_property DIRECTION OUT [get_ports LPDDR_out[0]cke_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[0]cke_a]
set_property SLEW FAST [get_ports LPDDR_out[0]cke_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]cke_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]cke_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]cke_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]cke_a]
set_property DIRECTION OUT [get_ports LPDDR_out[0]cke_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[0]cke_b]
set_property SLEW FAST [get_ports LPDDR_out[0]cke_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]cke_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]cke_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]cke_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]cke_b]
set_property DIRECTION OUT [get_ports LPDDR_out[0]cs_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[0]cs_a]
set_property SLEW FAST [get_ports LPDDR_out[0]cs_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]cs_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]cs_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]cs_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]cs_a]
set_property DIRECTION OUT [get_ports LPDDR_out[0]cs_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[0]cs_b]
set_property SLEW FAST [get_ports LPDDR_out[0]cs_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]cs_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]cs_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]cs_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]cs_b]
set_property DIRECTION OUT [get_ports LPDDR_out[0]reset_n]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[0]reset_n]
set_property SLEW FAST [get_ports LPDDR_out[0]reset_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[0]reset_n]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[0]reset_n]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[0]reset_n]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[0]reset_n]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[7]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[6]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[5]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[4]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[3]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[2]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[1]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_p[0]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[7]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[6]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[5]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[4]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[3]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[2]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[1]}]
set_property DIRECTION OUT [get_ports {PCIE0_GT_0_gtx_n[0]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[7]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[6]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[5]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[4]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[3]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[2]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[1]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_p[0]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[7]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[6]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[5]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[4]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[3]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[2]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[1]}]
set_property DIRECTION IN [get_ports {PCIE0_GT_0_grx_n[0]}]
set_property DIRECTION IN [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property ODT RTT_NONE [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_in[0][sys_clk_p][0][0]}]
set_property DIRECTION IN [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property ODT RTT_NONE [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_in[0][sys_clk_n][0][0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_t_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_t_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_c_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_c_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_t_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_t_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_c_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dqs_c_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[15]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[14]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[13]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[12]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[11]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[10]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[9]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[8]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[7]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[6]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[5]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[4]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[3]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[2]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dq_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_a[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_a[0]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[5]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[5]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[5]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[5]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[5]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[5]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[5]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[4]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[4]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[4]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[4]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[4]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[4]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[4]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[3]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[3]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[3]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[3]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[3]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[3]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[3]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[2]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[2]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[2]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[2]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[2]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[2]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[2]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[1]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[1]}]
set_property DIRECTION OUT [get_ports {LPDDR_out[3]ca_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_out[3]ca_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_out[3]ca_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_out[3]ca_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_out[3]ca_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_out[3]ca_b[0]}]
set_property EQUALIZATION EQ_NONE [get_ports {LPDDR_out[3]ca_b[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dmi_a[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dmi_a[0]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dmi_b[1]}]
set_property DIRECTION INOUT [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property IOSTANDARD LVSTL_11 [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property SLEW FAST [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property ODT RTT_40 [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property PRE_EMPHASIS RDRV_NONE [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property EQUALIZATION EQ_LEVEL3 [get_ports {LPDDR_inout[3]dmi_b[0]}]
set_property DIRECTION OUT [get_ports LPDDR_inout[3]ck_c_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[3]ck_c_a]
set_property SLEW FAST [get_ports LPDDR_inout[3]ck_c_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[3]ck_c_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[3]ck_c_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[3]ck_c_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[3]ck_c_a]
set_property DIRECTION OUT [get_ports LPDDR_out[3]ck_t_a]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[3]ck_t_a]
set_property SLEW FAST [get_ports LPDDR_out[3]ck_t_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]ck_t_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]ck_t_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]ck_t_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]ck_t_a]
set_property DIRECTION OUT [get_ports LPDDR_inout[3]ck_c_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_inout[3]ck_c_b]
set_property SLEW FAST [get_ports LPDDR_inout[3]ck_c_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_inout[3]ck_c_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_inout[3]ck_c_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_inout[3]ck_c_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_inout[3]ck_c_b]
set_property DIRECTION OUT [get_ports LPDDR_out[3]ck_t_b]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports LPDDR_out[3]ck_t_b]
set_property SLEW FAST [get_ports LPDDR_out[3]ck_t_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]ck_t_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]ck_t_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]ck_t_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]ck_t_b]
set_property DIRECTION OUT [get_ports LPDDR_out[3]cke_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[3]cke_a]
set_property SLEW FAST [get_ports LPDDR_out[3]cke_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]cke_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]cke_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]cke_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]cke_a]
set_property DIRECTION OUT [get_ports LPDDR_out[3]cke_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[3]cke_b]
set_property SLEW FAST [get_ports LPDDR_out[3]cke_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]cke_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]cke_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]cke_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]cke_b]
set_property DIRECTION OUT [get_ports LPDDR_out[3]cs_a]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[3]cs_a]
set_property SLEW FAST [get_ports LPDDR_out[3]cs_a]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]cs_a]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]cs_a]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]cs_a]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]cs_a]
set_property DIRECTION OUT [get_ports LPDDR_out[3]cs_b]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[3]cs_b]
set_property SLEW FAST [get_ports LPDDR_out[3]cs_b]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]cs_b]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]cs_b]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]cs_b]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]cs_b]
set_property DIRECTION OUT [get_ports LPDDR_out[3]reset_n]
set_property IOSTANDARD LVSTL_11 [get_ports LPDDR_out[3]reset_n]
set_property SLEW FAST [get_ports LPDDR_out[3]reset_n]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports LPDDR_out[3]reset_n]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports LPDDR_out[3]reset_n]
set_property PRE_EMPHASIS RDRV_NONE [get_ports LPDDR_out[3]reset_n]
set_property EQUALIZATION EQ_NONE [get_ports LPDDR_out[3]reset_n]
set_property DIRECTION IN [get_ports gt_refclk0_0_clk_n]
set_property DIRECTION IN [get_ports gt_refclk0_0_clk_p]
set_property DIRECTION IN [get_ports lpddr4_clk2_clk_n]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports lpddr4_clk2_clk_n]
set_property ODT RTT_NONE [get_ports lpddr4_clk2_clk_n]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports lpddr4_clk2_clk_n]
set_property PRE_EMPHASIS RDRV_NONE [get_ports lpddr4_clk2_clk_n]
set_property EQUALIZATION EQ_LEVEL3 [get_ports lpddr4_clk2_clk_n]
set_property DIRECTION IN [get_ports lpddr4_clk2_clk_p]
set_property IOSTANDARD DIFF_LVSTL_11 [get_ports lpddr4_clk2_clk_p]
set_property ODT RTT_NONE [get_ports lpddr4_clk2_clk_p]
set_property OFFSET_CNTRL CNTRL_NONE [get_ports lpddr4_clk2_clk_p]
set_property PRE_EMPHASIS RDRV_NONE [get_ports lpddr4_clk2_clk_p]
set_property EQUALIZATION EQ_LEVEL3 [get_ports lpddr4_clk2_clk_p]

set_property PACKAGE_PIN U36 [get_ports SCL]
set_property PACKAGE_PIN V36 [get_ports SDA]
set_property IOSTANDARD LVCMOS15 [get_ports SCL]
set_property IOSTANDARD LVCMOS15 [get_ports SDA]
set_property PACKAGE_PIN L36 [get_ports sys_reset_n]
set_property IOSTANDARD LVCMOS15 [get_ports sys_reset_n]
set_property PACKAGE_PIN K35 [get_ports {i2cmux_rst[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {i2cmux_rst[0]}]
set_property PACKAGE_PIN T33 [get_ports {leds[0]}]
set_property PACKAGE_PIN U33 [get_ports {leds[1]}]
set_property PACKAGE_PIN U37 [get_ports {leds[2]}]
set_property PACKAGE_PIN V37 [get_ports {leds[3]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[2]}]
set_property IOSTANDARD LVCMOS15 [get_ports {leds[3]}]

set_property PACKAGE_PIN BN27 [get_ports {LPDDR_inout[1][dq_a][0]}]
set_property PACKAGE_PIN BM27 [get_ports {LPDDR_inout[1][dq_a][1]}]
set_property PACKAGE_PIN BK27 [get_ports {LPDDR_inout[1][dq_a][2]}]
set_property PACKAGE_PIN BL26 [get_ports {LPDDR_inout[1][dq_a][3]}]
set_property PACKAGE_PIN BM26 [get_ports {LPDDR_inout[1][dq_a][4]}]
set_property PACKAGE_PIN BJ25 [get_ports {LPDDR_inout[1][dq_a][5]}]
set_property PACKAGE_PIN BN26 [get_ports {LPDDR_inout[1][dq_a][6]}]
set_property PACKAGE_PIN BH25 [get_ports {LPDDR_inout[1][dq_a][7]}]
set_property PACKAGE_PIN BB28 [get_ports {LPDDR_inout[1][dq_a][8]}]
set_property PACKAGE_PIN BC29 [get_ports {LPDDR_inout[1][dq_a][9]}]
set_property PACKAGE_PIN BB30 [get_ports {LPDDR_inout[1][dq_a][10]}]
set_property PACKAGE_PIN BC30 [get_ports {LPDDR_inout[1][dq_a][11]}]
set_property PACKAGE_PIN AY29 [get_ports {LPDDR_inout[1][dq_a][12]}]
set_property PACKAGE_PIN BD28 [get_ports {LPDDR_inout[1][dq_a][13]}]
set_property PACKAGE_PIN BA28 [get_ports {LPDDR_inout[1][dq_a][14]}]
set_property PACKAGE_PIN BE28 [get_ports {LPDDR_inout[1][dq_a][15]}]
set_property PACKAGE_PIN BK26 [get_ports {LPDDR_inout[1][dqs_t_a][0]}]
set_property PACKAGE_PIN BL25 [get_ports {LPDDR_inout[1][dqs_c_a][0]}]
set_property PACKAGE_PIN BB27 [get_ports {LPDDR_inout[1][dqs_t_a][1]}]
set_property PACKAGE_PIN BC28 [get_ports {LPDDR_inout[1][dqs_c_a][1]}]
set_property PACKAGE_PIN BM28 [get_ports {LPDDR_out[1][ca_a][0]}]
set_property PACKAGE_PIN BL28 [get_ports {LPDDR_out[1][ca_a][1]}]
set_property PACKAGE_PIN BK31 [get_ports {LPDDR_out[1][ca_a][2]}]
set_property PACKAGE_PIN BL29 [get_ports {LPDDR_out[1][ca_a][3]}]
set_property PACKAGE_PIN BM31 [get_ports {LPDDR_out[1][ca_a][4]}]
set_property PACKAGE_PIN BN31 [get_ports {LPDDR_out[1][ca_a][5]}]
set_property PACKAGE_PIN BK30 [get_ports {LPDDR_out[1][cs_a][0]}]
set_property PACKAGE_PIN BL30 [get_ports {LPDDR_out[1][ck_t_a][0]}]
set_property PACKAGE_PIN BM29 [get_ports {LPDDR_out[1][ck_c_a][0]}]
set_property PACKAGE_PIN BN29 [get_ports {LPDDR_out[1][cke_a][0]}]
set_property PACKAGE_PIN BG26 [get_ports {LPDDR_inout[1][dmi_a][0]}]
set_property PACKAGE_PIN AY30 [get_ports {LPDDR_inout[1][dmi_a][1]}]
set_property PACKAGE_PIN BB26 [get_ports {LPDDR_inout[1][dq_b][0]}]
set_property PACKAGE_PIN BA25 [get_ports {LPDDR_inout[1][dq_b][1]}]
set_property PACKAGE_PIN BC25 [get_ports {LPDDR_inout[1][dq_b][2]}]
set_property PACKAGE_PIN AY26 [get_ports {LPDDR_inout[1][dq_b][3]}]
set_property PACKAGE_PIN BD24 [get_ports {LPDDR_inout[1][dq_b][4]}]
set_property PACKAGE_PIN BE25 [get_ports {LPDDR_inout[1][dq_b][5]}]
set_property PACKAGE_PIN AV25 [get_ports {LPDDR_inout[1][dq_b][6]}]
set_property PACKAGE_PIN AW26 [get_ports {LPDDR_inout[1][dq_b][7]}]
set_property PACKAGE_PIN AW29 [get_ports {LPDDR_inout[1][dq_b][8]}]
set_property PACKAGE_PIN AV30 [get_ports {LPDDR_inout[1][dq_b][9]}]
set_property PACKAGE_PIN AY27 [get_ports {LPDDR_inout[1][dq_b][10]}]
set_property PACKAGE_PIN AU29 [get_ports {LPDDR_inout[1][dq_b][11]}]
set_property PACKAGE_PIN AU27 [get_ports {LPDDR_inout[1][dq_b][12]}]
set_property PACKAGE_PIN AT28 [get_ports {LPDDR_inout[1][dq_b][13]}]
set_property PACKAGE_PIN AV28 [get_ports {LPDDR_inout[1][dq_b][14]}]
set_property PACKAGE_PIN BA27 [get_ports {LPDDR_inout[1][dq_b][15]}]
set_property PACKAGE_PIN AY24 [get_ports {LPDDR_inout[1][dqs_t_b][0]}]
set_property PACKAGE_PIN AW25 [get_ports {LPDDR_inout[1][dqs_c_b][0]}]
set_property PACKAGE_PIN AT29 [get_ports {LPDDR_inout[1][dqs_t_b][1]}]
set_property PACKAGE_PIN AU30 [get_ports {LPDDR_inout[1][dqs_c_b][1]}]
set_property PACKAGE_PIN BF27 [get_ports {LPDDR_out[1][ca_b][0]}]
set_property PACKAGE_PIN BK28 [get_ports {LPDDR_out[1][ca_b][1]}]
set_property PACKAGE_PIN BJ30 [get_ports {LPDDR_out[1][ca_b][2]}]
set_property PACKAGE_PIN BH30 [get_ports {LPDDR_out[1][ca_b][3]}]
set_property PACKAGE_PIN BJ29 [get_ports {LPDDR_out[1][ca_b][4]}]
set_property PACKAGE_PIN BH29 [get_ports {LPDDR_out[1][ca_b][5]}]
set_property PACKAGE_PIN AW28 [get_ports {LPDDR_out[1][cs_b][0]}]
set_property PACKAGE_PIN BH27 [get_ports {LPDDR_out[1][ck_t_b][0]}]
set_property PACKAGE_PIN BJ27 [get_ports {LPDDR_out[1][ck_c_b][0]}]
set_property PACKAGE_PIN BJ28 [get_ports {LPDDR_out[1][cke_b][0]}]
set_property PACKAGE_PIN AT26 [get_ports {LPDDR_inout[1][dmi_b][0]}]
set_property PACKAGE_PIN AV27 [get_ports {LPDDR_inout[1][dmi_b][1]}]
set_property PACKAGE_PIN BE29 [get_ports {LPDDR_out[1][reset_n][0]}]
set_property PACKAGE_PIN AY18 [get_ports {LPDDR_inout[3][dq_a][0]}]
set_property PACKAGE_PIN BA18 [get_ports {LPDDR_inout[3][dq_a][1]}]
set_property PACKAGE_PIN BB19 [get_ports {LPDDR_inout[3][dq_a][2]}]
set_property PACKAGE_PIN BB20 [get_ports {LPDDR_inout[3][dq_a][3]}]
set_property PACKAGE_PIN BB22 [get_ports {LPDDR_inout[3][dq_a][4]}]
set_property PACKAGE_PIN BC21 [get_ports {LPDDR_inout[3][dq_a][5]}]
set_property PACKAGE_PIN AY20 [get_ports {LPDDR_inout[3][dq_a][6]}]
set_property PACKAGE_PIN BA21 [get_ports {LPDDR_inout[3][dq_a][7]}]
set_property PACKAGE_PIN BN24 [get_ports {LPDDR_inout[3][dq_a][8]}]
set_property PACKAGE_PIN BJ23 [get_ports {LPDDR_inout[3][dq_a][9]}]
set_property PACKAGE_PIN BK23 [get_ports {LPDDR_inout[3][dq_a][10]}]
set_property PACKAGE_PIN BN25 [get_ports {LPDDR_inout[3][dq_a][11]}]
set_property PACKAGE_PIN BL24 [get_ports {LPDDR_inout[3][dq_a][12]}]
set_property PACKAGE_PIN BM24 [get_ports {LPDDR_inout[3][dq_a][13]}]
set_property PACKAGE_PIN BK25 [get_ports {LPDDR_inout[3][dq_a][14]}]
set_property PACKAGE_PIN BJ24 [get_ports {LPDDR_inout[3][dq_a][15]}]
set_property PACKAGE_PIN AY21 [get_ports {LPDDR_inout[3][dqs_t_a][0]}]
set_property PACKAGE_PIN BA22 [get_ports {LPDDR_inout[3][dqs_c_a][0]}]
set_property PACKAGE_PIN BG24 [get_ports {LPDDR_inout[3][dqs_t_a][1]}]
set_property PACKAGE_PIN BH24 [get_ports {LPDDR_inout[3][dqs_c_a][1]}]
set_property PACKAGE_PIN AU18 [get_ports {LPDDR_out[3][ca_a][0]}]
set_property PACKAGE_PIN AT19 [get_ports {LPDDR_out[3][ca_a][1]}]
set_property PACKAGE_PIN AV21 [get_ports {LPDDR_out[3][ca_a][2]}]
set_property PACKAGE_PIN AU20 [get_ports {LPDDR_out[3][ca_a][3]}]
set_property PACKAGE_PIN AV22 [get_ports {LPDDR_out[3][ca_a][4]}]
set_property PACKAGE_PIN AW22 [get_ports {LPDDR_out[3][ca_a][5]}]
set_property PACKAGE_PIN AT20 [get_ports {LPDDR_out[3][cs_a][0]}]
set_property PACKAGE_PIN AV18 [get_ports {LPDDR_out[3][ck_t_a][0]}]
set_property PACKAGE_PIN AW19 [get_ports {LPDDR_out[3][ck_c_a][0]}]
set_property PACKAGE_PIN AV19 [get_ports {LPDDR_out[3][cke_a][0]}]
set_property PACKAGE_PIN BA19 [get_ports {LPDDR_inout[3][dmi_a][0]}]
set_property PACKAGE_PIN BL23 [get_ports {LPDDR_inout[3][dmi_a][1]}]
set_property PACKAGE_PIN BM21 [get_ports {LPDDR_inout[3][dq_b][0]}]
set_property PACKAGE_PIN BK21 [get_ports {LPDDR_inout[3][dq_b][1]}]
set_property PACKAGE_PIN BL19 [get_ports {LPDDR_inout[3][dq_b][2]}]
set_property PACKAGE_PIN BN22 [get_ports {LPDDR_inout[3][dq_b][3]}]
set_property PACKAGE_PIN BM22 [get_ports {LPDDR_inout[3][dq_b][4]}]
set_property PACKAGE_PIN BM19 [get_ports {LPDDR_inout[3][dq_b][5]}]
set_property PACKAGE_PIN BL20 [get_ports {LPDDR_inout[3][dq_b][6]}]
set_property PACKAGE_PIN BN21 [get_ports {LPDDR_inout[3][dq_b][7]}]
set_property PACKAGE_PIN BB23 [get_ports {LPDDR_inout[3][dq_b][8]}]
set_property PACKAGE_PIN BA24 [get_ports {LPDDR_inout[3][dq_b][9]}]
set_property PACKAGE_PIN BB24 [get_ports {LPDDR_inout[3][dq_b][10]}]
set_property PACKAGE_PIN AU23 [get_ports {LPDDR_inout[3][dq_b][11]}]
set_property PACKAGE_PIN AV24 [get_ports {LPDDR_inout[3][dq_b][12]}]
set_property PACKAGE_PIN BC24 [get_ports {LPDDR_inout[3][dq_b][13]}]
set_property PACKAGE_PIN AT25 [get_ports {LPDDR_inout[3][dq_b][14]}]
set_property PACKAGE_PIN AU24 [get_ports {LPDDR_inout[3][dq_b][15]}]
set_property PACKAGE_PIN BN19 [get_ports {LPDDR_inout[3][dqs_t_b][0]}]
set_property PACKAGE_PIN BN20 [get_ports {LPDDR_inout[3][dqs_c_b][0]}]
set_property PACKAGE_PIN AW23 [get_ports {LPDDR_inout[3][dqs_t_b][1]}]
set_property PACKAGE_PIN AY23 [get_ports {LPDDR_inout[3][dqs_c_b][1]}]
set_property PACKAGE_PIN BJ20 [get_ports {LPDDR_out[3][ca_b][0]}]
set_property PACKAGE_PIN BK20 [get_ports {LPDDR_out[3][ca_b][1]}]
set_property PACKAGE_PIN BH22 [get_ports {LPDDR_out[3][ca_b][2]}]
set_property PACKAGE_PIN BJ22 [get_ports {LPDDR_out[3][ca_b][3]}]
set_property PACKAGE_PIN BH21 [get_ports {LPDDR_out[3][ca_b][4]}]
set_property PACKAGE_PIN BG21 [get_ports {LPDDR_out[3][ca_b][5]}]
set_property PACKAGE_PIN BB18 [get_ports {LPDDR_out[3][cs_b][0]}]
set_property PACKAGE_PIN BH20 [get_ports {LPDDR_out[3][ck_t_b][0]}]
set_property PACKAGE_PIN BJ19 [get_ports {LPDDR_out[3][ck_c_b][0]}]
set_property PACKAGE_PIN BG22 [get_ports {LPDDR_out[3][cke_b][0]}]
set_property PACKAGE_PIN BK22 [get_ports {LPDDR_inout[3][dmi_b][0]}]
set_property PACKAGE_PIN AT22 [get_ports {LPDDR_inout[3][dmi_b][1]}]
set_property PACKAGE_PIN BF28 [get_ports {LPDDR_out[3][reset_n][0]}]
set_property PACKAGE_PIN BD30 [get_ports {LPDDR_in[1][sys_clk_p][0]}]
set_property PACKAGE_PIN BE30 [get_ports {LPDDR_in[1][sys_clk_n][0]}]
set_property PACKAGE_PIN BM4 [get_ports {LPDDR_inout[0][dq_a][0]}]
set_property PACKAGE_PIN BN5 [get_ports {LPDDR_inout[0][dq_a][1]}]
set_property PACKAGE_PIN BM7 [get_ports {LPDDR_inout[0][dq_a][2]}]
set_property PACKAGE_PIN BN7 [get_ports {LPDDR_inout[0][dq_a][3]}]
set_property PACKAGE_PIN BL6 [get_ports {LPDDR_inout[0][dq_a][4]}]
set_property PACKAGE_PIN BK7 [get_ports {LPDDR_inout[0][dq_a][5]}]
set_property PACKAGE_PIN BL5 [get_ports {LPDDR_inout[0][dq_a][6]}]
set_property PACKAGE_PIN BL8 [get_ports {LPDDR_inout[0][dq_a][7]}]
set_property PACKAGE_PIN BE18 [get_ports {LPDDR_inout[0][dq_a][8]}]
set_property PACKAGE_PIN BF18 [get_ports {LPDDR_inout[0][dq_a][9]}]
set_property PACKAGE_PIN BC16 [get_ports {LPDDR_inout[0][dq_a][10]}]
set_property PACKAGE_PIN BD16 [get_ports {LPDDR_inout[0][dq_a][11]}]
set_property PACKAGE_PIN BB14 [get_ports {LPDDR_inout[0][dq_a][12]}]
set_property PACKAGE_PIN BE17 [get_ports {LPDDR_inout[0][dq_a][13]}]
set_property PACKAGE_PIN BB15 [get_ports {LPDDR_inout[0][dq_a][14]}]
set_property PACKAGE_PIN BF16 [get_ports {LPDDR_inout[0][dq_a][15]}]
set_property PACKAGE_PIN BM6 [get_ports {LPDDR_inout[0][dqs_t_a][0]}]
set_property PACKAGE_PIN BN6 [get_ports {LPDDR_inout[0][dqs_c_a][0]}]
set_property PACKAGE_PIN BD15 [get_ports {LPDDR_inout[0][dqs_t_a][1]}]
set_property PACKAGE_PIN BE16 [get_ports {LPDDR_inout[0][dqs_c_a][1]}]
set_property PACKAGE_PIN BL15 [get_ports {LPDDR_out[0][ca_a][0]}]
set_property PACKAGE_PIN BK16 [get_ports {LPDDR_out[0][ca_a][1]}]
set_property PACKAGE_PIN BK17 [get_ports {LPDDR_out[0][ca_a][2]}]
set_property PACKAGE_PIN BN17 [get_ports {LPDDR_out[0][ca_a][3]}]
set_property PACKAGE_PIN BM17 [get_ports {LPDDR_out[0][ca_a][4]}]
set_property PACKAGE_PIN BN16 [get_ports {LPDDR_out[0][ca_a][5]}]
set_property PACKAGE_PIN BM18 [get_ports {LPDDR_out[0][cs_a][0]}]
set_property PACKAGE_PIN BM14 [get_ports {LPDDR_out[0][ck_t_a][0]}]
set_property PACKAGE_PIN BN14 [get_ports {LPDDR_out[0][ck_c_a][0]}]
set_property PACKAGE_PIN BM16 [get_ports {LPDDR_out[0][cke_a][0]}]
set_property PACKAGE_PIN BN9 [get_ports {LPDDR_inout[0][dmi_a][0]}]
set_property PACKAGE_PIN BB16 [get_ports {LPDDR_inout[0][dmi_a][1]}]
set_property PACKAGE_PIN BL11 [get_ports {LPDDR_inout[0][dq_b][0]}]
set_property PACKAGE_PIN BN12 [get_ports {LPDDR_inout[0][dq_b][1]}]
set_property PACKAGE_PIN BL10 [get_ports {LPDDR_inout[0][dq_b][2]}]
set_property PACKAGE_PIN BM12 [get_ports {LPDDR_inout[0][dq_b][3]}]
set_property PACKAGE_PIN BJ10 [get_ports {LPDDR_inout[0][dq_b][4]}]
set_property PACKAGE_PIN BK10 [get_ports {LPDDR_inout[0][dq_b][5]}]
set_property PACKAGE_PIN BJ12 [get_ports {LPDDR_inout[0][dq_b][6]}]
set_property PACKAGE_PIN BK11 [get_ports {LPDDR_inout[0][dq_b][7]}]
set_property PACKAGE_PIN BA16 [get_ports {LPDDR_inout[0][dq_b][8]}]
set_property PACKAGE_PIN AY17 [get_ports {LPDDR_inout[0][dq_b][9]}]
set_property PACKAGE_PIN AY15 [get_ports {LPDDR_inout[0][dq_b][10]}]
set_property PACKAGE_PIN AV16 [get_ports {LPDDR_inout[0][dq_b][11]}]
set_property PACKAGE_PIN AU15 [get_ports {LPDDR_inout[0][dq_b][12]}]
set_property PACKAGE_PIN AT16 [get_ports {LPDDR_inout[0][dq_b][13]}]
set_property PACKAGE_PIN AW17 [get_ports {LPDDR_inout[0][dq_b][14]}]
set_property PACKAGE_PIN BA15 [get_ports {LPDDR_inout[0][dq_b][15]}]
set_property PACKAGE_PIN BM11 [get_ports {LPDDR_inout[0][dqs_t_b][0]}]
set_property PACKAGE_PIN BN11 [get_ports {LPDDR_inout[0][dqs_c_b][0]}]
set_property PACKAGE_PIN AT17 [get_ports {LPDDR_inout[0][dqs_t_b][1]}]
set_property PACKAGE_PIN AU17 [get_ports {LPDDR_inout[0][dqs_c_b][1]}]
set_property PACKAGE_PIN BH14 [get_ports {LPDDR_out[0][ca_b][0]}]
set_property PACKAGE_PIN BL14 [get_ports {LPDDR_out[0][ca_b][1]}]
set_property PACKAGE_PIN BJ17 [get_ports {LPDDR_out[0][ca_b][2]}]
set_property PACKAGE_PIN BH16 [get_ports {LPDDR_out[0][ca_b][3]}]
set_property PACKAGE_PIN BL18 [get_ports {LPDDR_out[0][ca_b][4]}]
set_property PACKAGE_PIN BK18 [get_ports {LPDDR_out[0][ca_b][5]}]
set_property PACKAGE_PIN AW16 [get_ports {LPDDR_out[0][cs_b][0]}]
set_property PACKAGE_PIN BH15 [get_ports {LPDDR_out[0][ck_t_b][0]}]
set_property PACKAGE_PIN BJ15 [get_ports {LPDDR_out[0][ck_c_b][0]}]
set_property PACKAGE_PIN BK15 [get_ports {LPDDR_out[0][cke_b][0]}]
set_property PACKAGE_PIN BL13 [get_ports {LPDDR_inout[0][dmi_b][0]}]
set_property PACKAGE_PIN AV15 [get_ports {LPDDR_inout[0][dmi_b][1]}]
set_property PACKAGE_PIN BF14 [get_ports {LPDDR_out[0][reset_n][0]}]
set_property PACKAGE_PIN AP11 [get_ports {LPDDR_inout[2][dq_a][0]}]
set_property PACKAGE_PIN AR12 [get_ports {LPDDR_inout[2][dq_a][1]}]
set_property PACKAGE_PIN AU14 [get_ports {LPDDR_inout[2][dq_a][2]}]
set_property PACKAGE_PIN AV13 [get_ports {LPDDR_inout[2][dq_a][3]}]
set_property PACKAGE_PIN AT13 [get_ports {LPDDR_inout[2][dq_a][4]}]
set_property PACKAGE_PIN AT14 [get_ports {LPDDR_inout[2][dq_a][5]}]
set_property PACKAGE_PIN AP12 [get_ports {LPDDR_inout[2][dq_a][6]}]
set_property PACKAGE_PIN AR13 [get_ports {LPDDR_inout[2][dq_a][7]}]
set_property PACKAGE_PIN BJ2 [get_ports {LPDDR_inout[2][dq_a][8]}]
set_property PACKAGE_PIN BJ5 [get_ports {LPDDR_inout[2][dq_a][9]}]
set_property PACKAGE_PIN BK5 [get_ports {LPDDR_inout[2][dq_a][10]}]
set_property PACKAGE_PIN BK2 [get_ports {LPDDR_inout[2][dq_a][11]}]
set_property PACKAGE_PIN BJ3 [get_ports {LPDDR_inout[2][dq_a][12]}]
set_property PACKAGE_PIN BK3 [get_ports {LPDDR_inout[2][dq_a][13]}]
set_property PACKAGE_PIN BL3 [get_ports {LPDDR_inout[2][dq_a][14]}]
set_property PACKAGE_PIN BL4 [get_ports {LPDDR_inout[2][dq_a][15]}]
set_property PACKAGE_PIN AN14 [get_ports {LPDDR_inout[2][dqs_t_a][0]}]
set_property PACKAGE_PIN AP15 [get_ports {LPDDR_inout[2][dqs_c_a][0]}]
set_property PACKAGE_PIN BJ7 [get_ports {LPDDR_inout[2][dqs_t_a][1]}]
set_property PACKAGE_PIN BK6 [get_ports {LPDDR_inout[2][dqs_c_a][1]}]
set_property PACKAGE_PIN AJ13 [get_ports {LPDDR_out[2][ca_a][0]}]
set_property PACKAGE_PIN AJ12 [get_ports {LPDDR_out[2][ca_a][1]}]
set_property PACKAGE_PIN AM15 [get_ports {LPDDR_out[2][ca_a][2]}]
set_property PACKAGE_PIN AL15 [get_ports {LPDDR_out[2][ca_a][3]}]
set_property PACKAGE_PIN AL14 [get_ports {LPDDR_out[2][ca_a][4]}]
set_property PACKAGE_PIN AM13 [get_ports {LPDDR_out[2][ca_a][5]}]
set_property PACKAGE_PIN AJ15 [get_ports {LPDDR_out[2][cs_a][0]}]
set_property PACKAGE_PIN AK13 [get_ports {LPDDR_out[2][ck_t_a][0]}]
set_property PACKAGE_PIN AL12 [get_ports {LPDDR_out[2][ck_c_a][0]}]
set_property PACKAGE_PIN AM12 [get_ports {LPDDR_out[2][cke_a][0]}]
set_property PACKAGE_PIN AP14 [get_ports {LPDDR_inout[2][dmi_a][0]}]
set_property PACKAGE_PIN BH4 [get_ports {LPDDR_inout[2][dmi_a][1]}]
set_property PACKAGE_PIN BE9 [get_ports {LPDDR_inout[2][dq_b][0]}]
set_property PACKAGE_PIN BA10 [get_ports {LPDDR_inout[2][dq_b][1]}]
set_property PACKAGE_PIN BC12 [get_ports {LPDDR_inout[2][dq_b][2]}]
set_property PACKAGE_PIN BE10 [get_ports {LPDDR_inout[2][dq_b][3]}]
set_property PACKAGE_PIN BD10 [get_ports {LPDDR_inout[2][dq_b][4]}]
set_property PACKAGE_PIN BD11 [get_ports {LPDDR_inout[2][dq_b][5]}]
set_property PACKAGE_PIN BB10 [get_ports {LPDDR_inout[2][dq_b][6]}]
set_property PACKAGE_PIN BF10 [get_ports {LPDDR_inout[2][dq_b][7]}]
set_property PACKAGE_PIN BH11 [get_ports {LPDDR_inout[2][dq_b][8]}]
set_property PACKAGE_PIN BG12 [get_ports {LPDDR_inout[2][dq_b][9]}]
set_property PACKAGE_PIN BG10 [get_ports {LPDDR_inout[2][dq_b][10]}]
set_property PACKAGE_PIN BE12 [get_ports {LPDDR_inout[2][dq_b][11]}]
set_property PACKAGE_PIN BF11 [get_ports {LPDDR_inout[2][dq_b][12]}]
set_property PACKAGE_PIN BH10 [get_ports {LPDDR_inout[2][dq_b][13]}]
set_property PACKAGE_PIN BG13 [get_ports {LPDDR_inout[2][dq_b][14]}]
set_property PACKAGE_PIN BH12 [get_ports {LPDDR_inout[2][dq_b][15]}]
set_property PACKAGE_PIN BC9 [get_ports {LPDDR_inout[2][dqs_t_b][0]}]
set_property PACKAGE_PIN BC10 [get_ports {LPDDR_inout[2][dqs_c_b][0]}]
set_property PACKAGE_PIN BG9 [get_ports {LPDDR_inout[2][dqs_t_b][1]}]
set_property PACKAGE_PIN BH9 [get_ports {LPDDR_inout[2][dqs_c_b][1]}]
set_property PACKAGE_PIN BA12 [get_ports {LPDDR_out[2][ca_b][0]}]
set_property PACKAGE_PIN BB11 [get_ports {LPDDR_out[2][ca_b][1]}]
set_property PACKAGE_PIN AY12 [get_ports {LPDDR_out[2][ca_b][2]}]
set_property PACKAGE_PIN BB12 [get_ports {LPDDR_out[2][ca_b][3]}]
set_property PACKAGE_PIN BA13 [get_ports {LPDDR_out[2][ca_b][4]}]
set_property PACKAGE_PIN AW13 [get_ports {LPDDR_out[2][ca_b][5]}]
set_property PACKAGE_PIN AR15 [get_ports {LPDDR_out[2][cs_b][0]}]
set_property PACKAGE_PIN AY9 [get_ports {LPDDR_out[2][ck_t_b][0]}]
set_property PACKAGE_PIN BA9 [get_ports {LPDDR_out[2][ck_c_b][0]}]
set_property PACKAGE_PIN AY14 [get_ports {LPDDR_out[2][cke_b][0]}]
set_property PACKAGE_PIN BC13 [get_ports {LPDDR_inout[2][dmi_b][0]}]
set_property PACKAGE_PIN BE13 [get_ports {LPDDR_inout[2][dmi_b][1]}]
set_property PACKAGE_PIN BG14 [get_ports {LPDDR_out[2][reset_n][0]}]
set_property PACKAGE_PIN BG17 [get_ports {LPDDR_in[0][sys_clk_p][0]}]
set_property PACKAGE_PIN BG18 [get_ports {LPDDR_in[0][sys_clk_n][0]}]
set_property PACKAGE_PIN AD9 [get_ports {pcie_rxn[0]}]
set_property PACKAGE_PIN AJ7 [get_ports {pcie_rxn[1]}]
set_property PACKAGE_PIN AE1 [get_ports {pcie_rxn[2]}]
set_property PACKAGE_PIN AG1 [get_ports {pcie_rxn[3]}]
set_property PACKAGE_PIN AL1 [get_ports {pcie_rxn[5]}]
set_property PACKAGE_PIN AN1 [get_ports {pcie_rxn[6]}]
set_property PACKAGE_PIN AR1 [get_ports {pcie_rxn[7]}]
set_property PACKAGE_PIN AU1 [get_ports {pcie_rxn[8]}]
set_property PACKAGE_PIN AW1 [get_ports {pcie_rxn[9]}]
set_property PACKAGE_PIN AY3 [get_ports {pcie_rxn[10]}]
set_property PACKAGE_PIN BA1 [get_ports {pcie_rxn[11]}]
set_property PACKAGE_PIN BB3 [get_ports {pcie_rxn[12]}]
set_property PACKAGE_PIN BC1 [get_ports {pcie_rxn[13]}]
set_property PACKAGE_PIN BE1 [get_ports {pcie_rxn[14]}]
set_property PACKAGE_PIN BG6 [get_ports {pcie_rxn[15]}]
set_property PACKAGE_PIN AC2 [get_ports {pcie_rxp[0]}]
set_property PACKAGE_PIN AD4 [get_ports {pcie_rxp[1]}]
set_property PACKAGE_PIN AE2 [get_ports {pcie_rxp[2]}]
set_property PACKAGE_PIN AG2 [get_ports {pcie_rxp[3]}]
set_property PACKAGE_PIN AJ2 [get_ports {pcie_rxp[4]}]
set_property PACKAGE_PIN AL2 [get_ports {pcie_rxp[5]}]
set_property PACKAGE_PIN AN2 [get_ports {pcie_rxp[6]}]
set_property PACKAGE_PIN AR2 [get_ports {pcie_rxp[7]}]
set_property PACKAGE_PIN AU2 [get_ports {pcie_rxp[8]}]
set_property PACKAGE_PIN AW2 [get_ports {pcie_rxp[9]}]
set_property PACKAGE_PIN AY4 [get_ports {pcie_rxp[10]}]
set_property PACKAGE_PIN BA2 [get_ports {pcie_rxp[11]}]
set_property PACKAGE_PIN BB4 [get_ports {pcie_rxp[12]}]
set_property PACKAGE_PIN BC2 [get_ports {pcie_rxp[13]}]
set_property PACKAGE_PIN BE2 [get_ports {pcie_rxp[14]}]
set_property PACKAGE_PIN BG2 [get_ports {pcie_rxp[15]}]
set_property PACKAGE_PIN AF8 [get_ports {sys_clk_n[0]}]
set_property PACKAGE_PIN AU6 [get_ports {sys_clk_n[1]}]
set_property PACKAGE_PIN AF9 [get_ports {sys_clk_p[0]}]
set_property PACKAGE_PIN AU7 [get_ports {sys_clk_p[1]}]
set_property PACKAGE_PIN AJ1 [get_ports {pcie_rxn[4]}]

